Altera Embedded Peripherals IP - Manual (Page 58)

JTAG UART Core
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Core Overview
The JTAG UART core with Avalon ® interface implements a method to communicate serial character
streams between a host PC and a Qsys system on an Altera ® FPGA. In many designs, the JTAG UART
core eliminates the need for a separate RS-232 serial connection to a host PC for character I/O. The core
provides an Avalon interface that hides the complexities of the JTAG interface from embedded software
programmers. Master peripherals (such as a Nios ® II processor) communicate with the core by reading
and writing control and data registers.
The JTAG UART core uses the JTAG circuitry built in to Altera FPGAs, and provides host access via the
JTAG pins on the FPGA. The host PC can connect to the FPGA via any Altera JTAG download cable,
such as the USB-Blaster
™
cable. Software support for the JTAG UART core is provided by Altera. For the
Nios II processor, device drivers are provided in the hardware abstraction layer (HAL) system library,
allowing software to access the core using the ANSI C Standard Library
stdio.h
routines.
Nios II processor users can access the JTAG UART via the Nios II IDE or the nios2-terminal command-
line utility.
Nios II Software Developer's Handbook
For further details, refer to the or the Nios II IDE online help.
For the host PC, Altera provides JTAG terminal software that manages the connection to the target,
decodes the JTAG data stream, and displays characters on screen.
The JTAG UART core is Qsys-ready and integrates easily into any Qsys-generated system.
Functional Description
The figure below shows a block diagram of the JTAG UART core and its connection to the JTAG circuitry
inside an Altera FPGA. The following sections describe the components of the core.
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