Altera Embedded Peripherals IP - Manual (Page 323)

Error Register
The Error register bit is set automatically only when the associated message data word location that
contains the write entry, indicating it was dropped due to maximum entry limit reached. The Error bit
indicates the possibility of the MSI TLP targeting the associated system-specified address. This condition
should not happen as each MSI capable function is only allowed to send up to 32 MSI even with multiple
vector supported.
The Error bit can be cleared by the host processor by writing ‘1’ to the location.
Upon reset, the default value of the Error register bits are set to ‘0’.
The following table illustrates the Pending register field.
Table 33-3: Error Register fields
Field Name Bit Location
Error bit for message data word location [31:1] 31:1
Error bit for message data word location [0] 0
Interrupt Mask Register
The Interrupt Mask register provides a masking bit to individual Status bit before the Status is used to
generate level interrupt output. Having the masking bit set, disregards the corresponding Status bit from
causing interrupt output.
Upon reset, the default value of Interrupt Mask register is 0, which means every single data word address
location is disabled for interrupt generation. To enable interrupt generation from a dedicated message
entry location, the associated Mask bit needs to be set to ‘1’.
The following table illustrates the Interrupt Mask register field.
Table 33-4: Interrupt Mask Register fields
Field Name Bit Location
Masking bit for Status [31:1] 31:1
Masking bit for Status [0] 0
Unsupported Feature
The message data entry Avalon-MM Slave represents the system-specified address for MSI function. The
offset seen by MSI function should be similar to the offset seen by the host processors. As this Avalon-
MM Slave interface is accessible (write and read) by both the host processor and the PCIe RP HIP, any
read transaction to the offset address (system-specified address) is considered to have the message data
entry consumed. Observing this limitation, only host master, which is expected to serve the MSI should
read from the Avalon-MM Slave interface. A read from the PCIe RP_Master to the Avalon-MM Slave is
prohibited.
33-4 Error Register
UG-01085
2014.24.07
Altera Corporation Altera MSI to GIC Generator
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