Altera Embedded Peripherals IP - Manual (Page 123)

PIO Core
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Core Overview
The parallel input/output (PIO) core with Avalon ® interface provides a memory-mapped interface
between an Avalon ® Memory-Mapped (Avalon-MM) slave port and general-purpose I/O ports. The I/O
ports connect either to on-chip user logic, or to I/O pins that connect to devices external to the FPGA.
The PIO core provides easy I/O access to user logic or external devices in situations where a “bit banging”
approach is sufficient. Some example uses are:
• Controlling LEDs
• Acquiring data from switches
• Controlling display devices
• Configuring and communicating with off-chip devices, such as application-specific standard products
(ASSP)
The PIO core interrupt request (IRQ) output can assert an interrupt based on input signals.
Functional Description
Each PIO core can provide up to 32 I/O ports. An intelligent host such as a microprocessor controls the
PIO ports by reading and writing the register-mapped Avalon-MM interface. Under control of the host,
the PIO core captures data on its inputs and drives data to its outputs. When the PIO ports are connected
directly to I/O pins, the host can tristate the pins by writing control registers in the PIO core. The example
below shows a processor-based system that uses multiple PIO cores to drive LEDs, capture edges from on-
chip reset-request control logic, and control an off-chip LCD display.
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