Interrupt behavior, Performance counter api, Perf_reset() – Altera Embedded Peripherals IP User Manual

Page 306: Interrupt behavior -6, Performance counter api -6, Perf_reset() -6

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Table 31-5: Example 2:

--Performance Counter Report--

Total Time: 2.07711 seconds (103855534 clock-cycles)

+-----------------+--------+-----------+---------------+-----------+

| Section | % | Time (sec)| Time (clocks) |Occurrences|

+-----------------+--------+-----------+---------------+-----------+

|1st checksum_test| 50 | 1.03800 | 51899750 | 1 |

+-----------------+--------+-----------+---------------+-----------+

| pc_overhead |1.73e-05| 0.00000 | 18 | 1 |

+-----------------+--------+-----------+---------------+-----------+

| ts_overhead |4.24e-05| 0.00000 | 44 | 1 |

+-----------------+--------+-----------+---------------+-----------+

For full documentation of

perf_print_formatted_report()

, see the Performance and Counter API

section.

Interrupt Behavior

The performance counter core does not generate interrupts.
You can start and stop performance counters, and read raw performance results, in an interrupt service

routine (ISR). Do not call the

perf_print_formatted_report()

function from an ISR.

If an interrupt occurs during the measurement of a section of code, the time taken by the CPU to process

the interrupt and return to the section is added to the measurement time. The same applies to context

switches in a multithreaded environment. Your software must take appropriate measures to avoid or

handle these situations.

Performance Counter API

This section describes the application programming interface (API) for the performance counter core.
For Nios

II processor users, Altera provides routines to access the performance counter core hardware.

These functions are specific to the performance counter core and directly manipulate low level hardware.

The performance counter core cannot be accessed via the HAL API or the ANSI C standard library.

PERF_RESET()

Prototype:

PERF_RESET(p)

Thread-safe:

Yes.

Available

from ISR:

Yes.

Include:

<altera_avalon_performance_counter.h>

Parameters:

p

—performance counter core base address.

31-6

Interrupt Behavior

UG-01085

2014.24.07

Altera Corporation

Performance Counter Core

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