Altera Embedded Peripherals IP - Manual (Page 148)

The PCI testbench includes the following features:
• Easy to use simulation environment for any standard Verilog HDL simulator
• Open source Verilog HDL files
• Flexible PCI bus functional model to verify your application that uses any PCI Lite core
• Simulates all basic PCI transactions including memory read/write operations, I/O read/write transac‐
tions, and configuration read/write transactions
• Simulates all abnormal PCI transaction terminations including target retry, target disconnect, target
abort, and master abort
• Simulates PCI bus parking
Master Transactor (mstr_tranx)
The master transactor simulates the master behavior on the PCI bus. It serves as an initiator of PCI
transactions for PCI testbench. The master transactor has three main sections:
• TASKS (Verilog HDL)
• INITIALIZATION
• USER COMMANDS
Figure 14-4: TASKS Sections
The TASKS (Verilog HDL) sections define the events that are executed for the user commands
supported by the master transactor. The events written in the TASKS sections follow the phases of a
standard PCI transaction as defined by the PCI Local Bus Specification, Revision 3.0, including:
• Address phase
• Turn-around phase (read transactions)
• Data phases
• Turn-around phase
The master transactor terminates the PCI transactions in the following cases:
• The PCI transaction has successfully transferred all the intended data.
• The PCI target terminates the transaction prematurely with a target retry, disconnect, or abort as
defined in the PCI Local Bus Specification, Revision 3.0.
• A target does not claim the transaction resulting in a master abort.
The bus monitor informs the master transactor of a successful data transaction or a target termination.
Refer to the source code, which shows you how the master transactor uses these termination signals
from the bus monitor.
The PCI testbench master transactor TASKS sections implement basic PCI transaction functionality. If
your application requires different functionality, modify the events to change the behavior of the
master transactor. Additionally, you can create new procedures or tasks in the master transactor by
using the existing events as an example.
INITIALIZATION Section
This user-defined section defines the parameters and reset length of your PCI bus on power-up. Specifi‐
cally, the system should reset the bus and write the configuration space of the PCI agents. You can modify
the master transactor INITIALIZATION section to match your system requirements by changing the
time that the system reset is asserted and by modifying the data written in the configuration space of the
PCI agents.
14-14 Master Transactor (mstr_tranx)
UG-01085
2014.24.07
Altera Corporation PCI Lite Core
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