System reset considerations, Instantiating the avalon altpll core, Instantiating the pll core – Altera Embedded Peripherals IP User Manual

Page 314: System reset considerations -3, Instantiating the avalon altpll core -3, Instantiating the pll core -3

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or control signals which are not mapped to registers are exported to the top-level module. For details,

refer to the Instantiating the Avalon ALTPLL Core.

System Reset Considerations

At FPGA configuration, the PLL cores reset automatically. PLL-specific reset circuitry guarantees that the

PLL locks before releasing reset for the overall SOPC Builder system module.
Resetting the PLL resets the entire SOPC Builder system module.

Instantiating the Avalon ALTPLL Core

When you instantiate the Avalon ALTPLL core, the MegaWizard Plug-In Manager is automatically

launched for you to parameterize the ALTPLL megafunction. There are no additional parameters that you

can configure in SOPC Builder.
The

pfdena

signal of the ALTPLL megafunction is not exported to the top level of the SOPC Builder

module. You can drive this port by writing to the

PFDENA

bit in the

control

register.

The

locked

,

pllena

/

extclkena

, and

areset

signals of the megafunction are always exported to the top

level of the SOPC Builder module. You can read the

locked

signal and reset the core by manipulating

respective bits in the registers. See the Register Definitions and Bit List section for more information on

the registers.
For details about using the ALTPLL MegaWizard Plug-In Manager, refer to the

ALTPLL Megafunction

User Guide

.

Instantiating the PLL Core

This section describes the options available in the MegaWizard

interface for the PLL core in SOPC

Builder.

PLL Settings Page

The PLL Settings page contains a button that launches the ALTPLL MegaWizard Plug-In Manager. Use

the MegaWizard Plug-In Manager to parameterize the ALTPLL megafunction. The set of available

parameters depends on the target device family.
You cannot click Finish in the PLL wizard nor configure the PLL interface until you parameterize the

ALTPLL megafunction.

Interface Page

The Interface page configures the access modes for the optional advanced PLL status and control signals.

UG-01085

2014.24.07

System Reset Considerations

32-3

PLL Cores

Altera Corporation

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