Avalon-to-pci read request, Ordering of requests, Ordering of requests -9 – Altera Embedded Peripherals IP User Manual
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Termination condition
Resulting Action
Avalon-to-PCI command/write
data buffer running out of data
Normal master-initiated termination on the PCI bus.
Master controller waits for the buffer to reach 8
DWORD
s on a
32-bit PCI or 16
DWORD
s on a 64-bit PCI, or there is enough
data to complete the remaining burst count. Once enough
data is available, the master controller arbiter continues wth
the PCI write.
PCI target disconnect
The master controller arbiter attempts to initiate the PCI
write until the transaction is successful.
PCI target retry
PCI target-abort
The rest of the write data is read from the buffer and
discarded.
PCI master-abort
Avalon-to-PCI Read Request
For read requests from the interconnect, the request is pushed on the PCI bus by a configuration read, I/O
read, memory read, memory read line, or memory read multiple command. The PCI read is issued to
configuration, I/O, or memory space based on the address translation table entry. See Avalon-to-PCI
Address Translation section.
If a memory space read request can be completed in a single data phase, it is issued as a memory read
command. If the memory space read request spans more than one data phase but does not cross a
cacheline boundary (as defined by the cacheline size register), it is issued as a memory read line
command. If the memory space read request crosses a cache line boundary, it is issued as multiple
memory read commands.
Read requests on PCI may initially be retried. Retries depend on the response time from the target. The
master continues to retry until it gets the required data.
Table 14-8: PCI Master Read Request Termination Conditions
Termination Condition
Resulting Action
Burst count
satisfied
Normal master initiated termination on the PCI bus. Master controller
proceeds to the next command.
Latency timer
expired
Normal master initiated termination on PCI bus. The continuation of the
PCI read is made pending as a request from the master controller arbiter.
PCI target
disconnect
The continuation of the PCI read is requested from the master controller
arbiter.
PCI target retry
PCI target-abort
Dummy data is returned to complete the Avalon-MM read request. The next
operation is then attempted in a normal fashion.
PCI master-abort
Ordering of Requests
The PCI-Avalon bridge handles the following types of requests:
UG-01085
2014.24.07
Avalon-to-PCI Read Request
14-9
PCI Lite Core
Altera Corporation