Altera Embedded Peripherals IP - Manual (Page 71)

Avalon-MM Slave Interface and Registers
The UART core provides an Avalon-MM slave interface to the internal register file. The user interface to
the UART core consists of six, 16-bit registers:
control
,
status
,
rxdata
,
txdata
,
divisor
, and
endofpacket
. A master peripheral, such as a Nios II processor, accesses the registers to control the core
and transfer data over the serial connection.
The UART core provides an active-high interrupt request (IRQ) output that can request an interrupt
when new data has been received, or when the core is ready to transmit another character. For further
details, refer to the Interrupt Behavior section.
The Avalon-MM slave port is capable of transfers with flow control. The UART core can be used in
conjunction with a direct memory access (DMA) peripheral with Avalon-MM flow control to automate
continuous data transfers between, for example, the UART core and memory.
For more information, refer to Interval Timer Core section.
For details about the Avalon-MM interface, refer to the
Avalon Interface Specifications.
RS-232 Interface
The UART core implements RS-232 asynchronous transmit and receive logic. The UART core sends and
receives serial data via the
TXD
and
RXD
ports. The I/O buffers on most Altera FPGA families do not
comply with RS-232 voltage levels, and may be damaged if driven directly by signals from an RS-232
connector. To comply with RS-232 voltage signaling specifications, an external level-shifting buffer is
required (for example, Maxim MAX3237) between the FPGA I/O pins and the external RS-232 connector.
The UART core uses a logic 0 for mark, and a logic 1 for space. An inverter inside the FPGA can be used
to reverse the polarity of any of the RS-232 signals, if necessary.
Transmitter Logic
The UART transmitter consists of a 7-, 8-, or 9-bit
txdata
holding register and a corresponding 7-, 8-, or
9-bit transmit shift register. Avalon-MM master peripherals write the
txdata
holding register via the
Avalon-MM slave port. The transmit shift register is loaded from the
txdata
register automatically when
a serial transmit shift operation is not currently in progress. The transmit shift register directly feeds the
TXD
output. Data is shifted out to
TXD
LSB first.
These two registers provide double buffering. A master peripheral can write a new value into the
txdata
register while the previously written character is being shifted out. The master peripheral can monitor the
transmitter's status by reading the
status
register's transmitter ready (
TRDY
), transmitter shift register
empty (
tmt
), and transmitter overrun error (
TOE
) bits.
The transmitter logic automatically inserts the correct number of start, stop, and parity bits in the serial
TXD
data stream as required by the RS-232 specification.
Receiver Logic
The UART receiver consists of a 7-, 8-, or 9-bit receiver-shift register and a corresponding 7-, 8-, or 9-bit
rxdata
holding register. Avalon-MM master peripherals read the
rxdata
holding register via the Avalon-
MM slave port. The
rxdata
holding register is loaded from the receiver shift register automatically every
time a new character is fully received.
These two registers provide double buffering. The
rxdata
register can hold a previously received
character while the subsequent character is being shifted into the receiver shift register.
8-2 Avalon-MM Slave Interface and Registers
UG-01085
2014.24.07
Altera Corporation UART Core
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