Altera Embedded Peripherals IP - Manual (Page 127)

Edge Capture Register
Turn on Synchronously capture to include the edge capture register,
edgecapture
, in the core. The edge
capture register allows the core to detect and generate an optional interrupt when an edge of the specified
type occurs on an input port. The user must further specify the following features:
• Select the type of edge to detect:
• Rising Edge
• Falling Edge
• Either Edge
• Turn on Enable bit-clearing for edge capture register to clear individual bit in the edge capture
register. To clear a given bit, write 1 to the bit in the edge capture register.
Interrupt
Turn on Generate IRQ to assert an IRQ output when a specified event occurs on input ports. The user
must further specify the cause of an IRQ event:
• Level— The core generates an IRQ whenever a specific input is high and interrupts are enabled for
that input in the
interruptmask
register.
• Edge— The core generates an IRQ whenever a specific bit in the edge capture register is high and
interrupts are enabled for that bit in the
interruptmask
register.
When Generate IRQ is off, the
interruptmask
register does not exist.
Simulation
The Simulation page allows you to specify the value of the input ports during simulation. Turn on
Hardwire PIO inputs in test bench to set the PIO input ports to a certain value in the testbench, and
specify the value in Drive inputs to field.
Software Programming Model
This section describes the software programming model for the PIO core, including the register map and
software constructs used to access the hardware. For Nios ® II processor users, Altera provides the HAL
system library header file that defines the PIO core registers. The PIO core does not match the generic
device model categories supported by the HAL, so it cannot be accessed via the HAL API or the ANSI C
standard library.
The Nios II Embedded Design Suite (EDS) provides several example designs that demonstrate usage of
the PIO core. In particular, the count_binary.c example uses the PIO core to drive LEDs, and detect button
presses using PIO edge-detect interrupts.
Software Files
The PIO core is accompanied by one software file, altera_avalon_pio_regs.h . This file defines the core's
register map, providing symbolic constants to access the low-level hardware.
Register Map
An Avalon-MM master peripheral, such as a CPU, controls and communicates with the PIO core via the
four 32-bit registers, shown below. The table assumes that the PIO core's I/O ports are configured to a
width of n bits.
UG-01085
2014.24.07
Edge Capture Register 12-5
PIO Core Altera Corporation
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