Altera Embedded Peripherals IP - Manual (Page 295)

Core Behavior
The Avalon-ST JTAG Interface core is supported when used with the System Console; a Tcl console that
provides access to IP cores instantiated in your Qsys system.
The Avalon-ST JTAG Interface core supports two sets of operations:
• Bytestream
• JTAG debug
Bytestream Operation
The bytestream operation uses the System Console’s bytestream service. This operation allows you to
configure the core to send and receive a stream of bytes through the Avalon-ST interfaces.
Table 29-2: Bytestream Commands
Command Description Operation
bytestream_send
Sends a stream of bytes down to the
Avalon-ST source interface.
The stream of byte that appears
on the Avalon-ST source interface
is in the same order as sent from
the JTAG host.
bytestream_
receive
Receives a stream of bytes from the
Avalon-ST sink interface.
The stream of bytes that appears
on the JTAG host is in the same
order as sent from the Avalon-ST
sink interface.
JTAG Debug Operation
The JTAG debug operation uses the System Console’s JTAG debug service. This operation allows you to
configure the core to to debug the clock and reset signals, issue a reset, and verify the signal integrity of
the JTAG chain.
Table 29-3: JTAG Debug Commands
Command Description Operation
jtag_debug_loop
Verifies the signal integrity of the
JTAG chain by making sure the
data sent are the same as the data
received.
The bytes received from the
JTAG interface are looped-
back through an internal
register.
jtag_debug_reset_
system
Issues a reset to the external system
with its reset signal connected to
the
resetrequest
output signal.
The output signal,
resetre-
quest
, is asserted high for at
least one second.
jtag_debug_sample_
clock
Samples the clock (
clk
) signal to
verify that the clock is toggling.
The input clock signal is
sampled once.
jtag_debug_sample_
reset
Samples the reset (
reset_n
) signal
to verify that the signal is not tied
to ground.
The input reset signal is
sampled once.
jtag_debug_sense_clock
Senses the clock signal to verify that
the clock is toggling.
An internal register is set on
the clock’s rising edge if the
clock is toggling.
29-2 Core Behavior
UG-01085
2014.24.07
Altera Corporation Avalon-ST JTAG Interface Core
Send Feedback