Altera Embedded Peripherals IP - Manual (Page 97)

Qsys generation, that is to say once FIFO Depth is selected the depth for the FIFO can’t be change
anymore.
Table 9-12: Supported Features
Features Run Time Generate Time
FIFO/ FIFO-less mode Yes Yes
FIFO Depth - Yes
Programmable Tx/Rx FIFO
Threshold
Yes -
5-8 bit character length Yes -
1, 1.5, 2 character stop bit Yes -
Parity enable Yes -
Even/Odd parity Yes -
Baud rate selection Yes -
Priority based interrupt with configu‐
rable enable
Yes -
Hardware Auto Flow Control Yes Yes
Unsupported Features
The 16550 UART driver does not support Software flow control.
Configuration
The figure below shows the Qsys setup on the 16550 Soft-UART's FIFO Depth
UG-01085
2014.24.07
Unsupported Features 9-11
16550 UART Altera Corporation
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