Asynchronous transmit – Zilog Z80230 User Manual
Page 100
SCC/ESCC
User Manual
UM010903-0515
Data Communication Modes
93
The SCC supports Asynchronous mode with a number of programmable options including the
number of bits per character, the number of stop bits, the clock factor, modem interface signals,
and break detect and generation.
Asynchronous mode is selected by programming the desired number of stop bits in D3 and D2 of
WR4. Programming these two bits with other than 00 places both the receiver and transmitter in
Asynchronous mode. In this mode, the SCC ignores the state of bits D4, D3, and D2 of WR3, bits
D5 and D4 of WR4, bits D2 and D0 of WR5, all of WR6 and WR7, and all of WR10 except D6
and D5. Ignored bits are programmed with 1 or 0 (
Asynchronous Transmit
Asynchronous mode is selected by specifying the number of stop bits per character in bits D3 and
D2 of WR4. The three options available are one, one-and-a-half, and two stop bits per character.
These two bits select only the number of stop bits for the transmitter, as the receiver always checks
for one stop bit.
The number of bits per transmitted character is controlled both by bits D6 and D5 in WR5 and the
way the data is formatted within the transmit buffer (in the case of the ESCC, Transmit FIFO). The
bits in WR5 allow the option of five, six, seven, or eight bits per character. In all cases the data
must be right-justified, with the unused bits being ignored except in the case of five bits per char-
acter. When the five bits per character option is selected, the data may be formatted before being
written to the transmit buffer. This allows transmission of from one to five bits per character. The
formatting is listed in
Write Register Bits Ignored in Asynchronous Mode
Register
D7
D6
D5 D4 D3 D2 D1
D0
WR3
x
x
x
0
WR4
x
x
WR5
x
x
WR6
x
x
x
x
x
x
x
x
WR7
x
x
x
x
x
x
x
x
WR10
x
x
x
x
x
x
Note: If WR3 D1 is set (enabling the sync character load inhibit feature),
any character matching the value in WR6 is stripped out of the incoming
data stream and not put into the Receive FIFO. Therefore, as this feature
is typically only desired in synchronous formats, this bit should reset in
Asynchronous mode.