Zilog Z80230 - Manual (Page 238)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
231
Interrupt Acknowledge Cycle Timing
The primary timing differences between the Z180 and SCC occur in the Interrupt Acknowledge
cycle. The SCC timing parameters that are significant during Interrupt Acknowledge cycles are in
Table on page 231. The Z180 timing parameters are in Table . The reference numbers in Table
and Table refer to Figure on page 230.
10 MHz SCC Timing Parameters for Interrupt Acknowledge Cycle
No Symbol Parameter Min Max Units
13 TsIAi(RD) /INTACK Low to /RD Low
Setup
130 ns
14 ThIA(RD) /INTACK High to /RD
High Hold
0 ns
15 ThIA(PC) /INTACK to PCLK High
Hold
30 ns
38 TwRDA /INTACK Low to /RD Low
Delay (Acknowledge)
125 ns
39 TwRDA /RD (Acknowledge) Width 125 ns
40 TdRDA(DR) /RD Low (Acknowledge)
to Read Data Valid Delay
120 ns
41 TsIEI(RDA) IEI to /RD Low
(Acknowledge) Setup
Time
95 ns
42 ThIEI(RDA) IEI to /RD High
(Acknowledge) Hold Time
0 ns
43 TdIEI(IEO) IEI to IEO Delay 175 ns