Zilog Z80230 - Manual (Page 40)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
33
for the 85230/L, while Figure on page 29 displays the register bit location for the 85C30. Note
that the difference between the two WR7' registers for the 85230/L and the 85C30 is bit D5 and bit
D4. All writes to address seven are to WR7' when WR15 D0=1. Refer to Register Descriptions on
page 136 for detailed information on WR7'.
Write Register 7 Prime (WR7') for the 85230/L
Write Register 7 Prime for the 85C30
D7 D6 D5 D4 D3 D2 D1 D0
WR7'
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Rx FIFO Half Full
DTR/REQ Timing Mode
Tx FIFO Empty
Extended Read Enable
Reserved (Must be 0)
D7 D6 D5 D4 D3 D2 D1 D0
WR7' Prime
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Force TxD High
/DTR//REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)