Zilog Z80230 - Manual (Page 41)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
34
Setting WR7' bit D6=1 enables the extended read register capability. This allows the user to read
the contents of WR3, WR4, WR5, WR7' and WR10 by reading RR9, RR4, RR5, RR14 and RR11,
respectively. When WR7' D6=0, these write registers are write-only.
Table lists what functions are enabled for the various combinations of register bit enables. See
Table on page 31 for the register address map with only the SDLC FIFO enabled and with both
the extended read and SDLC FIFO features enabled.
Z85X30 Reset
The Z85X30 may be reset by either a hardware or software reset. Hardware reset occurs when /
WR and /RD are both Low at the same time, which is normally an illegal condition.
As long as both /WR and /RD are Low, the Z85X30 recognizes the reset condition. However, once
this condition is removed, the reset condition is asserted internally for an additional four to five
PCLK cycles. During this time any attempt to access is ignored.
The Z85X30 has three software resets that are encoded into the command bits in WR9. There are
two channel resets which only affect one channel in the device and some bits of the write registers.
The command forces the same result as the hardware reset, the Z85X30 stretches the reset signal
an additional four to five PCLK cycles beyond the ordinary valid access recovery time. The bits in
WR9 may be written at the same time as the reset command because these bits are affected only by
a hardware reset. The reset values of the various registers are listed in Table .
Z85C30/Z85230/L Register Enhancement Options
WR15 WR7’
Bit D2 Bit D0 Bit D6 Functions Enabled
0 1 0 WR7' enabled only
0 1 1 WR7' with extended read enabled
1 0 X 10x19 SDLC FIFO enhancement enabled only
1 1 0 10x19 SDLC FIFO and WR7'
1 1 1 10x19 SDLC FIFO and WR7' with extended read
enabled