Zilog Z80230 User Manual

Page 161

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SCC/ESCC

User Manual

UM010903-0515

Register Descriptions

154

Bit 2: SDLC/CRC-16 polynomial select bit

This bit selects the CRC polynomial used by both the transmitter and receiver. When set, the CRC-

16 polynomial is used; when reset, the SDLC polynomial is used. The SDLC/CRC polynomial is

selected when SDLC mode is selected. The CRC generator and checker can be preset to all 0s or

all 1s, depending on the state of the Preset 1/Preset 0 bit in WR10.

Bit 1: Request To Send control bit

This is the control bit for the /RTS pin. When the RTS bit is set, the /RTS pin goes Low; when

reset, /RTS goes High. When Auto Enable is set in asynchronous mode, the /RTS pin immediately

goes Low when the RTS bit is set. However, when the RTS bit is reset, the /RTS pin remains Low

until the transmitter is completely empty and the last stop bit has left the TxD pin. In synchronous

modes, the /RTS pin directly follows the state of this bit, except in SDLC mode under specific

conditions. In SDLC mode, if Flag On Underrun bit (WR10, D2) is set, RTS bit in WR5 is reset,

and D2 in WR7' is set. The /RTS pin deasserts automatically at the last bit of the closing flag trig-

gered by the rising edge of the Tx clock. This bit is reset by a channel or hardware reset.

Bit 0: Transmit CRC Enable

This bit determines whether or not the CRC is calculated on a transmit character. If this bit is set at

the time the character is loaded from the transmit buffer to the Transmit Shift register, the CRC is

calculated on that character. The CRC is not automatically sent unless this bit is set when the

transmit underrun exists.

Write Register 6 (Sync Characters or SDLC Address Field)

WR6 is programmed to contain the transmit sync character in the Monosync mode, or the first

byte of a 16bit sync character in the External Sync mode. WR6 is not used in asynchronous

modes. In the SDLC modes, it is programmed to contain the secondary address field used to com-

pare against the address field of the SDLC Frame. In SDLC mode, the SCC does not automatically

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