Zilog Z80230 - Manual (Page 49)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
42
• IP is set without a higher priority IUS being set
• No higher priority IUS is being set
• No higher priority interrupt is being serviced (IEI is High)
• No interrupt acknowledge transaction is taking place
IEO is not pulled Low by the SCC at this time, but instead continues to follow IEI until an inter-
rupt acknowledge transaction occurs. Some time after /INT has been pulled Low, the processor
initiates an Interrupt Acknowledge transaction. Between the time the SCC recognizes that an
Interrupt Acknowledge cycle is in progress and the time during the acknowledge that the proces-
sor requests an interrupt vector, the IEI/IEO daisy chain settles. Any peripheral in the daisy chain
having an Interrupt Pending (IP is 1) or an Interrupt-Under-Service (IUS is 1) holds its IEO line
Low and all others make IEO follow IEI.
When the processor requests an interrupt vector, only the highest priority interrupt source with a
pending interrupt (IP is 1) has its IEI input High, its IE bit set to 1, and its IUS bit set to 0. This is
the interrupt source being acknowledged, and at this point it sets its IUS bit to 1. If its NV bit is 0,
the SCC identifies itself by placing the interrupt vector from WR2 on the data bus. If the NV bit is
1, the SCC data bus remains floating, allowing external logic to supply a vector. If the VIS bit in
the SCC is 1, the vector also contains status information, encoded as listed in Table , which further
lists the nature of the SCC interrupt.
Interrupt Vector Modification
If the VIS bit is 0, the vector held in WR2 is returned without modification. If the SCC is pro-
grammed to include status information in the vector, this status may be encoded and placed in
either bits 1-3 or in bits 4-6. This operation is selected by programming the Status High/Status
Low bit in WR9. At the end of the interrupt service routine, the processor should issue the Reset
Highest IUS command to unlock the daisy chain and allow lower priority interrupt requests. The
IP is reset during the interrupt service routine, either directly by command or indirectly through
V3 V2 V1 Status High/Status Low = 0
V4 V5 V6 Status High/Status Low = 1
0 0 0 Ch B Transmit Buffer Empty
0 0 1 Ch B External/Status Change
0 1 0 Ch B Receive Character Avail
0 1 1 Ch B Special Receive Condition
1 0 0 Ch A Transmit Buffer Empty
1 0 1 Ch A External/Status Change
1 1 0 Ch A Receive Character Avail
1 1 1 Ch A Special Receive Condition