Zilog Z80230 - Manual (Page 33)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
26
Z80X30 Reset
The Z80X30 may be reset by either a hardware or software reset. Hardware reset occurs when /AS
and /DS are both Low at the same time, which is normally an illegal condition.
As long as both /AS and /DS are Low, the Z80X30 recognizes the reset condition. However, once
this condition is removed, the reset condition is asserted internally for an additional four to five
PCLK cycles. During this time, any attempt to access is ignored.
The Z80X30 has three software resets that are encoded into two command bits in WR9. There are
two channel resets, which only affect one channel in the device and some bits of the write regis-
ters. The command forces the same result as the hardware reset, the Z80X30 stretches the reset
signal an additional four to five PCLK cycles beyond the ordinary valid access recovery time. The
bits in WR9 may be written at the same time as the reset command because these bits are affected
only by a hardware reset. The reset values of the various registers are listed in Table .
Z80230 SDLC/HDLC Enhancement Options
WR15 WR7’
Bit D2 Bit D0 Bit D6 Functions Enabled
0 1 0 WR7' enabled only
0 1 1 WR7' with extended read enabled
1 0 X 10x19 SDLC FIFO enhancement enabled only
1 1 0 10x19 SDLC FIFO and WR7'
1 1 1 10x19 SDLC FIFO and WR7' with extended read
enabled
Z80X30 Register Reset Values
Hardware RESET Channel RESET
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
WR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WR1 0 0 X 0 0 X 0 0 0 0 X 0 0 X 0 0
WR2 X X X X X X X X X X X X X X X X
WR3 X X X X X X X 0 X X X X X X X 0
WR4 X X X X X 1 X X X X X X X 1 X X
WR5 0 X X 0 0 0 0 X 0 X X 0 0 0 0 X