Zilog Z80230 - Manual (Page 136)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
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go directly to the bus interface (the FIFO pointer logic is reset either when disabled or via a chan-
nel or Power-On Reset). The FIFO mode is disabled on power-up (WR15 D2 is set to 0 on reset).
The effects of backward compatibility on the register set are that RR4 is an image of RR0, RR5 is
an image of RR1, RR6 is an image of RR2 and RR7 is an image of RR3. For the details of the
added registers, see Register Descriptions on page 136. The status of the FIFO Enable signal can
be obtained by reading RR15 bit D2. If the FIFO is enabled, the bit is set to 1; otherwise, it is reset.
Read Operation.
When WR15 bit D2 is set and the FIFO is not empty, the next read to any of sta-
tus register RR1 or the additional registers RR7 and RR6 is from the FIFO. Reading status register
RR1 causes one location of the FIFO to be emptied, so status is read after reading the byte count,
otherwise the count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multi-
plexer is switched to allow status to read directly from the status register, and reads from RR7 and
RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) is used to determine if
status data is coming from the FIFO or directly from the status register, since it is set to 1 when-
ever the FIFO is not empty.
Since not all status bits are stored in the FIFO, the All Sent, Parity, and EOF bits bypass the FIFO.
The status bits sent through the FIFO are Residue Bits (3), Overrun, and CRC Error.
The sequence for proper operation of the byte count and FIFO logic is to read the register in the
following order: RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents the
FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the FIFO
empty/full status bit (D6) and steers the status multiplexer to read from the CMOS/ESCC mega-
cell instead of the status FIFO (since the status FIFO is empty). The read from RR1 allows an
entry to be read from the FIFO (if the FIFO was empty, logic was added to prevent a FIFO under-
flow condition).
Write Operation.
When the end of an SDLC frame (EOF) has been received and the FIFO is
enabled, the contents of the status and byte-count registers are loaded into the FIFO. The EOF sig-
nal is used to increment the FIFO. If the FIFO overflows, the RR7 bit D7 (FIFO Overflow) is set
to indicate the overflow. This bit and the FIFO control logic is reset by disabling and re-enabling
the FIFO control bit (WR15 bit 2). For details of FIFO control timing during an SDLC frame, see
Figure .