Zilog Z80230 - Manual (Page 13)

SCC/ESCC
User Manual
UM010903-0515 General Description
6
SCC Block Diagram
Transmit Log
Channel A
Receive and Transmit Clock Mul
Transmit FIFO
NMOS/CMOS: 1 b
ESCC: 4 Bytes
Transmit MU
Data Encoding & CR
Generation
Digital
Phase-Locke
Loop
Baud Rat
Generato
Crystal
Oscillato
Amplifie
Modem/Control Lo
Receive MU
CRC Checke
Data Decode &
Sync Charact
Detection
Rec. Status*
FIFO
Rec. Data*
FIFO
SDLC Frame Status F
10 x 19
Receive Log
TxDA
/TRxCA
/RTxCA
/CTSA
/DCDA
/SYNCA
/RTSA
/DTRA//REQ
RxDA
Interna
Contro
Logic
Channel A
Register
Channel B
Register
Interrup
Control
Logic
CPU & DMA
Bus Interfac
Databu
Contro
Channel A
Channel B
/IN
/INTAC
IE
IEO
Interru
Contro
Exploded Vie
** See No
* NMOS/CMOS: 3 bytes each
ESCC: 8 bytes
** Not Available on NMOS