Zilog Z80230 - Manual (Page 132)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
125
In addition to searching the data stream for flags, the receiver in the SCC also watches for seven
consecutive 1s, which is the abort condition. The presence of seven consecutive 1s is reported in
the Break/Abort bit in RR0. This is one of the possible external/status interrupts, so transitions of
this status may be programmed to cause interrupts. Upon receipt of an abort the receiver is forced
into Hunt mode where it looks for flags. The Hunt status is also a possible external/status condi-
tion whose transition may be programmed to cause an interrupt. The transitions of these two bits
occur very close together, but either one or two external/status interrupts may result. The abort
condition is terminated when a 0 is received, either by itself or as the leading 0 of a flag. The
receiver does not leave Hunt mode until a flag has been received, so two discrete external/status
conditions occur at the end of an abort. An abort received in the middle of a frame terminates the
frame reception, but not in an orderly manner because the character being assembled is lost.
Up to two modem control signals associated with the receiver are available in SDLC mode:
• The /DTR//REQ pin carries an inverted state of the DTR bit (D7) in WR5 unless this pin
has been programmed to carry a DMA Request signal.
• The /DCD pin is ordinarily a simple input to the DCD bit in RR0. However, if the Auto
Enables mode is selected by setting bit D5 of WR3 to 1, this pin becomes an enable for the
receiver. That is, if Auto Enables is on and the /DCD pin is High, the receiver is disabled.
While the /DCD pin is Low, the receiver is enabled.
SDLC Initialization.
The initialization sequence for SDLC mode is WR4 to select SDLC mode
first, WR3 and WR5 to select the various options, WR7 to program flag, and then WR6 for the
receive address. At this point the other registers should be initialized as necessary. When all this is
completed the receiver is enabled by setting bit D0 of WR3 to a one. A summary is listed in Table
on page 125.
Initializing in SDLC Mode
Bit#
Reg D7 D6 D5 D4 D3 D2 D1 D0 Description
WR4 0
0 1 0 0 0 0 0 Select x1 clock, SDLC mode, enable sync
mode
WR3 r x 0 1 1 1 0 0 rx=# of Rx bits/char, No auto enable, enter
Hunt. Enable Rx CRC, Address Search, No
sync character load inhibit
WR5 d t x 0 0 0 r 1 d=inverse of DTR pin, tx=# of Tx bits/char,
use SDLC CRC, r=inverse state of /RTS pin,
CRC enable
WR7 0 1 1 1 1 1 1 0 SDLC Flag
WR6 x x x x x x x x Receiver secondary address