Zilog Z80230 User Manual
Page 277
SCC/ESCC
User Manual
UM010903-0515
Application Notes
270
J23-J1 thru -3
1 to 2: (E)SCC B RxRQ on DMA 0
2 to 3: (E)SCC B Wait function
(E)SCC B neither RxDMA
nor Wait
J24-J1 thru -4
1 to 2: clipped SCC B TxREQ on DMA1
1 to 3: direct ESCC B TxREQ on DMA1
3 to 4: DTR output from ESCC B
(E)SCC B neither TxDMA
nor DTR
J25-J1 thru -5 and
J25X
1 to 2 and 3 to 4: (E)SCC last on IACK chain
MUSC second to last
J25X to 2 and 3 to 4: (E)SCC last, USC second
to last
2 to 3 and 4 to 5: (E)SCC first on IACK chain
Must be one of these three ways
J28-J1 thru -6
1 to 2: 80186 SYSCLK is (E)SCC PCLK
3 to 4: 80186 SYSCLK is ISCC PCLK
5 to 6: 80186 SYSCLK is IUSC PCLK
Connect some other clock to 2, 4,
or 6
J29-J1 thru -4
1 to 2: USC B RxREQ on DMA0
1 to 3: USC B RxREQ on DMA1
2 to 4: USC B TxREQ on DMA0
3 to 4: USC B TxREQ on DMA1
1: USC B Rx no DMA
4: USC B Tx no DMA
Two-Pin Option Jumpers (Continued)
Jumpers
Installed
Open