An0096: the z180 interfaced with the scc at 10 mhz – Zilog Z80230 User Manual

Page 217

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SCC/ESCC

User Manual

UM010903-0515

Application Notes

210

AN0096: The Z180 Interfaced with the SCC at 10 MHz

Abstract

This Application Note describes how to build a simple system to prove and test Zilog’s Z180

Microprocessor Unit (MPU) interfacing Zilog’s Serial Communications Controller (SCC) at 

10 MHz. Replacing Zilog’s Z80

®

with the Z180 provides higher integration, reduced parts, more

board space, increased processing speed, and greater reliability.
It also describes the design of a system using Z80180 MPU and Z85C30 SCC, both running at 10

MHz. Hereinafter, all references are to the Z180 and SCC.

Features

The system board is a vehicle for demonstration and evaluation of the 10 MHz interface and

includes the following parts:

Z8018010VSC Z180 MPU 10 MHz, PLCC package

Z85C3010VSC C-MOS Z8530 SCC, 10 MHz, PLCC package

27C256 EPROM

55257 Static RAM

Discussion

Zilog’s Z180 is a Z80-compatible High Integration device with various peripherals on-board.

Using this device as an alternative to the Z80 CPU, reduces the number of parts and board space

while increasing processing speed and reliability.
The serial communication devices on the Z180 include:

1. Two asynchronous channels.
2. One clocked serial channel.

This means handling synchronous serial communications protocols requires an off-chip ‘multi-

protocol SCC.’ The SCC is the ideal device for this purpose.
SCC is the multi-protocol (@ 10 MHz) universal serial communication controller which supports

most serial communication applications including Monosync, Bisync and SDLC at 2.5 Mbps

speeds. Further, the wide acceptance of this device by the market ensures it is an ‘industry stan-

dard’ SCC. Also, the Z180 has special numbers for system clock frequencies of 6.144 and 9.216

MHz which generate exact baud rates for on-chip asynchronous serial communication channels.

This is due to the SCC’s on-chip, 16-bit wide baud rate generator for asynchronous ASCI commu-

nications.
The following 10 MHz interface explanation defines how the interrupt structure works. Also

included is a discussion of the hardware and software considerations involved in running the sys-

tem’s communication board. This application note is written for a reader with strong working

knowledge of the Z180 and SCC. It is not a tutorial for each device.

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