Zilog Z80230 - Manual (Page 174)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
167
Bit 2: TRxC Pin I/O control bit
This bit determines the direction of the /TRxC pin. If this bit is set to 1, the /TRxC pin is an output
and carries the signal selected by D1 and D0 of this register. However, if either the receive or the
transmit clock is programmed to come from the /TRxC pin, /TRxC is an input, regardless of the
state of this bit. The /TRxC pin is also an input if this bit is set to 0. A hardware reset forces this bit
to 0.
Bits 1 and 0: /TRxC Output Source select bits 1 and 0
These bits determine the signal to be echoed out of the SCC via the /TRxC pin as listed in Table
on page 167. No signal is produced if /TRxC has been programmed as the source of either the
receive or the transmit clock. If /TRxC O/I (bit 2) is set to 0, these bits are ignored.
If the XTAL oscillator output is programmed to be echoed, and the XTAL oscillator is not enabled,
the /TRxC pin goes High. The DPLL signal that is echoed is the DPLL signal used by the receiver.
Hardware reset selects the XTAL oscillator as the output source.
Write Register 12 (Lower Byte of Baud Rate Generator Time Constant)
WR12 contains the lower byte of the time constant for the baud rate generator. The time constant
can be changed at any time, but the new value does not take effect until the next time the time con-
stant is loaded into the down counter. No attempt is made to synchronize the loading of the time
constant into WR12 and WR13 with the clock driving the down counter. For this reason, it is
Transmit Clock Source
Bit 4 Bit 3 Transmit Clock
0 0 /RTxC P in
0 1 /TRxC P in
1 0 BR Output
1 1 DPLL Output
Transmit External Control Selection
Bit 1 Bit 0 TRxC Pin Output
0 0 XTAL Oscillator Output
0 1 Transmit Clock
1 0 BR Output
1 1 DPLL Output (receive)