Zilog Z80230 - Manual (Page 131)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
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the top of the FIFO can cause a special receive condition. The processor then reads RR1 to deter-
mine the result of the CRC calculation and the Residue Code.
Only the CRC-CCITT polynomial is used for CRC calculations in SDLC mode, although the gen-
erator and checker can be preset to all 1s or all 0s. The CRC-CCITT polynomial is selected by set-
ting bit D2 of WR5 to 0. Bit D7 of WR10 controls the preset value. If this bit is set to 1, the
generator and checker are preset to 1s, and if this bit is reset, the generator and checker are preset
to all 0s.
The receiver expects the CRC to be inverted before transmission, so it checks the CRC result
against the value 0001110100001111. The SCC presets the CRC checker whenever the receiver is
in Hunt mode or whenever a flag is received, so a CRC reset command is not necessary. However,
the CRC checker can be preset by issuing the Reset CRC Checker command in WR0.
The CRC checker is automatically enabled for all data between the opening and closing flags by
the SCC in SDLC mode, and the Rx CRC Enable bit (D3) in WR3 is ignored. The result of the
CRC calculation for the entire frame is valid in RR1 only when accompanied by the End of Frame
bit set in RR1. At all other times, the CRC Error bit in RR1 should be ignored by the processor.
On the NMOS/CMOS version, care must be exercised so that the processor does not attempt to use
the CRC bytes that are transferred as data, because not all of the bits are transferred properly. The
last two bits of CRC are never transferred to the receive data FIFO and are not recoverable.
On the ESCC, an enhancement has been made allowing the 2nd byte of the CRC to be received
completely. This feature is useful when the application requires the 2nd CRC byte as data. For
example, applications which operate in transparent mode or protocols using the error checking
mechanism other than CRC-CCITT (like 32-bit CRC).
Note the following about SCC CRC operation:
• The normal CRC checking mechanism involves checking over data and CRC characters.
If the division remainder is 0, there is no CRC error.
• SDLC is different. The CRC generator, when receiving a correct frame, has a fixed, non-
zero remainder. The actual remainder in the receive CRC calculation is checked against
this fixed value to determine if a CRC error exists.
A frame is terminated by a closing flag. When the SCC recognizes this flag:
• The contents of the Receive Shift register are transferred to the receive data FIFO.
• The Residue Code is latched, the CRC Error bit is latched in the status FIFO and the End
of Frame bit is set in the receive status FIFO.
The End of Frame bit, upon reaching the exit location of the FIFO, will cause a special receive
condition. The processor may then read RR1 to determine the result of the CRC calculation as
well as the Residue Code. If either the Rx Interrupt on Special Condition Only or the Rx Interrupt
on First Character or Special Condition modes are selected, the processor must issue an Error
Reset command in WR0 to unlock the Receive FIFO.