Zilog Z80230 - Manual (Page 191)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
184
If the FIFO overflows, the FIFO and the FIFO Overflow Status bit are cleared by disabling and
then re-enabling the FIFO through the FIFO control bit (WR15, D2). Otherwise, this register
returns an image of RR3.
On the NMOS version, a read to this location returns an image of RR3.
Read Register 8
RR8 is the Receive Data register.
Read Register 9 (ESCC and 85C30 Only)
On the ESCC, Read Register 9 reflects the contents of Write Register 3 provided the Extended
Read option has been enabled.
On the NMOS/CMOS version, a read to this location returns an image of RR13.
Read Register 7 FIFO Status Decoding
Bit D7 FIFO Data Available Status
1 Status reads come from FIFO (FIFO is
not Empty)
0 Status reads bypass FIFO because
FIFO is Empty)
Bit D6 FIFO Overflow Status
1 FIFO has overflowed
0 Normal operation