Zilog Z80230 - Manual (Page 86)

SCC/ESCC
User Manual
UM010903-0515 SCC/ESCC Ancillary Support Circuitry
79
WR14 (7-5) = 110 selects FM mode
A channel or hardware reset disables the DPLL, selects the /RTxC pin as the clock source
for the DPLL, and places it in the NRZI mode.
As in the case of the clock source selection, the mode of operation is only changed while the
DPLL is disabled to prevent unpredictable results.
In the NRZI mode, the DPLL clock must be 32 times the data rate. In this mode, the transmit and
receive clock outputs of the DPLL are identical, and the clocks are phased so that the receiver
samples the data in the middle of the bit cell. In NRZI mode, the DPLL does not require a transi-
tion in every bit cell, so this mode is useful for recovering the clocking information from NRZ and
NRZI data streams.
In the FM mode, the DPLL clock must be 16 times the data rate. In this mode, the transmit clock
output of the DPLL lags the receive clock outputs by 90 degrees to make the transmit and receive
bit cell boundaries the same, because the receiver must sample FM data at one-quarter and three-
quarters bit time.
The DPLL is enabled by issuing the Enter Search Mode command in WR14; that is WR14 (7-5) =
001. The Enter Search Mode command unlocks the counter, which is held while the DPLL is dis-
abled, and enables the edge detector. If the DPLL is already enabled when this command is issued,
the DPLL also enters Search Mode.
DPLL Operation in the NRZI Mode
To operate in NRZI mode, the DPLL must be supplied with a clock that is 32 times the data rate.
The DPLL uses this clock, along with the receive data, to construct receive and transmit clock out-
puts that are phased to properly receive and transmit data.
To do this, the DPLL divides each bit cell into four regions, and makes an adjustment to the count
cycle of the 5-bit counter dependent upon the region a transition on the receive data input occurred
( Figure on page 80).
Ordinarily, a bit-cell boundary occurs between count 15 and count 16, and the DPLL output causes
the data to be sampled in the middle of the bit cell. However, four different situations can occur:
If the bit-cell boundary (from space to mark) occurs anywhere during the second half of count 15
or the first half of count 16, the DPLL allows the transition without making a correction to its
count cycle.
If the bit cell boundary (from space to mark) occurs between the middle of count 16 and count 31,
the DPLL is sampling the data too early in the bit cell. In response to this, the DPLL extends its
count by one during the next 0 to 31 counting cycle, which effectively moves the edge of the clock
that samples the receive data closer to the center of the bit cell.
If the transition occurs between count 0 and the middle of count 15, the output of the DPLL is
sampling the data too late in the bit cell. To correct this, the DPLL shortens its count by one during
Note: