Zilog Z80230 - Manual (Page 149)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
142
nal/Status Interrupt has not yet been issued) and this condition persists until after the command is
issued, this second change causes another External/Status interrupt. However, if this second status
change does not persist (there are two transitions), another interrupt is not generated. Exceptions
to this rule are detailed in the RR0 description.
Send Abort Command (011).
This command is used in SDLC mode to transmit a sequence of
eight to thirteen 1s. This command always empties the transmit buffer and sets Tx Underrun/EOM
bit in Read Register 0.
Enable Interrupt On Next Rx Character Command (100).
If the interrupt on First Received
Character mode is selected, this command is used to reactivate that mode after each message is
received. The next character to enter the Receive FIFO causes a Receive interrupt. Alternatively,
the first previously stored character in the FIFO causes a Receive interrupt.
Reset Tx Interrupt Pending Command (101).
This command is used in cases where there are no
more characters to be sent; e.g., at the end of a message. This command prevents further transmit
interrupts until after the next character has been loaded into the transmit buffer or until CRC has
been completely sent. This command is necessary to prevent the transmitter from requesting an
interrupt when the transmit buffer becomes empty (with Transmit Interrupt Enabled).
Error Reset Command (110).
This command resets the error bits in RR1. If interrupt on first Rx
Character or Interrupt on Special Condition modes is selected and a special condition exists, the
data with the special condition is held in the Receive FIFO until this command is issued. If either
of these modes is selected and this command is issued before the data has been read from the
Receive FIFO, the data is lost.
Reset Highest IUS Command (110).
This command resets the highest priority Interrupt Under
Service (IUS) bit, allowing lower priority conditions to request interrupts. This command allows
the use of the internal daisy chain (even in systems without an external daisy chain) and is the last
operation in an interrupt service routine.
Bits 2 through 0: Register Selection Code
On the Z85X30, these three bits select Registers 0 through 7. With the Point High command, Reg-
isters 8 through 15 are selected (See Table on page 144).
In the multiplexed bus mode, bits D2 through D0 have the following function.
Bit D2 must be programmed as 0. Bits D1 and D0 select Shift Left/Right; that is WR0 (1-0)=10 for
shift left and WR0 (1-0)=11 for shift right. See Section 2.1.4 for further details on Z80X30 register
access.
Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode
Definition)
Write Register 1 is the control register for the various SCC interrupt and Wait/Request modes.
Figure displays the bit assignments for WR1.
Bit 7: WAIT/DMA Request Enable.