Zilog Z80230 - Manual (Page 21)

SCC/ESCC
User Manual
UM010903-0515 General Description
14
is OFF, the /RTS pins are used as general-purpose outputs, and, they strictly follow the inverse
state of WR5, bit D1.
ESCC and 85C30:
In SDLC mode, the /RTS pins can be programmed to be deasserted when the closing flag of the
message clears the TxD pin, if WR7' D2 is set.
/SYNCA, /SYNCB
. Synchronization (inputs or outputs, active Low). These pins can act either as
inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal
oscillator option not selected), these pins are inputs similar to CTS and DCD. In this mode, transi-
tions on these lines affect the state of the Synchronous/Hunt status bits in Read Register 0 but have
no other function. With the crystal oscillator option selected, these /SYNCA, /SYNCB pins
become the oscillator Xout pins and /RTxCA, /RTxCB pins become the Xin pins, respectively.
In External Synchronization mode, with the crystal oscillator not selected, these lines also act as
inputs. In this mode, /SYNC is driven Low to receive clock cycles after the last bit in the synchro-
nous character is received. Character assembly begins on the rising edge of the receive clock
immediately preceding the activation of SYNC.
In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator not
selected, these pins act as outputs and are active only during the part of the receive clock cycle in
which the synchronous condition is not latched. These outputs are active each time a synchroniza-
tion pattern is recognized (regardless of character boundaries). In SDLC mode, the pins act as out-
puts and are valid on receipt of a flag. The /SYNC pins switch from input to output when
monosync, bisync, or SDLC is programmed in WR4 and sync modes are enabled.
/DTR//REQA, /DTR//REQB
. Data Terminal Ready/Request (outputs, active Low). These pins
are programmable (WR14, D2) to serve either as general-purpose outputs or as DMA Request
lines. When programmed for DTR function (WR14 D2=0), these outputs follow the state pro-
grammed into the DTR bit of Write Register 5 (WR5 D7). When programmed for Ready mode,
these pins serve as DMA Requests for the transmitter.
ESCC and 85C30:
When used as DMA request lines (WR14, D2=1), the timing for the deactivation request can be
programmed in the added register, Write Register 7' (WR7') bit D4. If this bit is set, the /DTR//
REQ pin is deactivated with the same timing as the /W/REQ pin. If WR7' D4 is reset, the deactiva-
tion timing of /DTR//REQ pin is four clock cycles, the same as in the Z85C30.
/W//REQA, /W//REQB.
Wait/Request (outputs, open-drain when programmed for Wait function,
driven High or Low when programmed for Ready function). These dual-purpose outputs may be
programmed as Request lines for a DMA controller or as Wait lines to synchronize the CPU to the
SCC data rate. The reset state is Wait.
RxDA, RxDB.
Receive Data (inputs, active High). These input signals receive serial data at stan-
dard TTL levels.
/RTxCA, /RTxCB.
Receive/Transmit Clocks (inputs, active Low). These pins can be programmed
to several modes of operation. In each channel, /RTxC may supply the receive clock, the transmit