Zilog Z80230 - Manual (Page 144)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
137
WR15 External status interrupt enable control
Notes
1. ESCC and 85C30 only.
2. On the ESCC and 85C30, these registers are readable as RR9,
RR4, RR5, and RR11, respectively, when WR7' D6=1. Refer to
the description of WR7 Prime for enabling the extended read
capability.
3. This feature is not available on NMOS.
SCC Read Registers
Reg Description
RR0 Transmit and Receive buffer status and external status
RR1 Special Receive Condition status
RR2 Modified interrupt vector (Channel B only), Unmodified interrupt
vector (Channel A only)
RR3 Interrupt pending bits (Channel A only)
RR4 2 Transmit and Receive modes and parameters (WR4)
RR5 2 Transmit parameters and control modes (WR5)
RR6 3 SDLC FIFO byte counter lower byte (only when enabled)
RR7 3 SDLC FIFO byte count and status (only when enabled)
RR8 Receive buffer
RR9
2
Receive parameters and control modes (WR3)
RR10 Miscellaneous status bits
RR11 2 Miscellaneous transmit and receive control bits (WR10)
RR12 Lower byte of baud rate generator time constant
RR13 Upper byte of baud rate generator time constant
RR14 2 Extended Feature and FIFO Control (WR7 Prime)
SCC Write Registers (Continued)
Reg Description