Zilog Z80230 - Manual (Page 218)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
211
Interfaces
The following subsections explain the interfaces between the:
• Z180 and Memory
• Z180 and I/O
• Z180 and SCC
Basic goals of this system design are:
• System clock up to 10 MHz
• Using the Z8018010VSC (Z180 10 MHz PLCC package) to take advantage of 1 MB
addressing space and compactness (DIP versions’ addressing range is half; 512 KB)
• Using Z85C3010VSC (CMOS SCC 10 MHz PLCC package)
• Minimum parts count
• Worst case design
• Using EPLD for glue wherever possible
• Expendability
The design method for EPLD is using TTLs (74HCT) and then translating them into EPLD logic.
This design uses TTLs and EPLDs.
Z180 to Memory Interface
The memory access cycle timing of the Z180 is similar to the Z80
®
CPU memory access cycle
timing. The three classifications are:
• Opcode fetch cycle (Figure )
• Memory read cycle (Figure on page 213)
• Memory write cycle (Figure on page 216)