Zilog Z80230 - Manual (Page 54)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
47
When these bits indicate that a received character has reached the exit location of the FIFO, the
status in RR1 should be checked and then the data should be read. If status is to be checked, it
must be done before the data is read, because the act of reading the data pops both the data and
error FIFOs.
Receive Interrupt on First Character or Special Condition
This mode is designed for use with DMA transfers of the receive characters. The processor is
interrupted when the SCC receives the first character of a block of data. It reads the character and
then turns control over to a DMA device to transfer the remaining characters. After this mode is
selected, the first character received, or the first character already stored in the FIFO, sets the
receiver IP. This IP is reset when this character is removed from the SCC.
No further receive interrupts occur until the processor issues an Enable Interrupt on Next Receive
Character command in WR0 or until a special receive condition occurs. The correct sequence of
events when using this mode is to first select the mode and wait for the receive character available
interrupt. When the interrupt occurs, the processor should read the character and then enable the
DMA to transfer the remaining characters.
ESCC:
WR7' bit D3 should be reset to zero in this mode.
A special receive condition interrupt may occur any time after the first character is received, but is
guaranteed to occur after the character having the special condition has been read. The status is not
lost in this case, however, because the FIFO is locked by the special condition. In the interrupt ser-
vice routine, the processor should read RR1 to obtain the status, and may read the data again if
necessary. The FIFO is unlocked by issuing an Error Reset command in WR0. If the special condi-
tion was End-of-Frame, the processor should now issue the Enable Interrupt on Next Receive
Character command to prepare for the next frame. The first character interrupt and special condi-
tion interrupt are distinguished by the status included in the interrupt vector. In all other respects
they are identical, including sharing the IP and IUS bits.
Interrupt on All Receive Characters or Special Condition
This mode is designed for an interrupt driven system. In this mode, the NMOS/CMOS version and
the ESCC with WR7' D3=0 sets the receive IP when a received character is shifted into the exit
location of the FIFO. This occurs whether or not it has a special receive condition. This includes
characters already in the FIFO when this mode is selected. In this mode of operation the IP is reset
when the character is removed from the FIFO, so if the processor requires status for any charac-
ters, this status must be read before the data is removed from the FIFO.
On the ESCC with D3=1, four bytes are accumulated in the Receive FIFO before an interrupt is
generated (IP is set), and reset when the number of the characters in the FIFO is less than four.
The special receive conditions are identical to those previously mentioned, and as before, the only
difference between a “receive character available” interrupt and a “special receive condition”
interrupt is the status encoded in the vector. In this mode a special receive condition does not lock