Zilog Z80230 User Manual

Page 267

Advertising
background image

SCC/ESCC

User Manual

UM010903-0515

Application Notes

260

The MSB of the data (D7) is 1 to enable the Byte Swap feature, so that when the ISCC’s

DMA controller is reading transmit data from RAM, it takes alternate Bytes from AD7-

AD0 and AD15-AD8.

D6 of the data is 1 so that when the ISCC’s DMA controller is reading transmit data from

RAM, it takes even-addressed Bytes from D7-D0 and odd-addressed bytes from D15-D8

(same function as the 80186).

D2-D1 of the data are 11 to select double-pulsed mode for the ISCC’s INTACK input.

This is how the 80186 functions.

D0 of the data is 0 to select Shift Left Address mode so that the ISCC subsequently takes

register addressing from the AD5-AD1 lines rather than from AD4-AD0. This is because

the 80186 is a 16-bit processor that locates even-addressed Bytes on AD7-AD0 and odd-

addressed bytes on AD15-AD8, but the ISCC only accepts slave-mode writes on the AD7-

AD0 pins.

The ISCC’s internal logic detecting activity on its AS pin, which is inverted from the

80186 ALE signal, automatically conditions it for a multiplexed Address/Data bus. Given

that the BCR is written as previously described, the ISCC’s slave mode map is as listed in

Table .

(M)USC

Since the 80186 processor provides multiplexed addresses and data, the (M)USC is configured to

use the addresses on the AD lines. The software does not need to write register addresses into the

indirect address field of the (M)USC CCAR.
The (M)USC’s Transmitter and Receiver can be handled on a polled or interrupt-driven basis. In

addition, and two of the Receivers and Transmitters in the (M)USC and Channel B of the (E)SCC

can be handled on a DMA basis, using the 80186’s integrated controllers.
Jumper block J22 connects the (M)USC’s RxREQ and TxREQ outputs to the

DMA

EPLD

that

makes the DMA Requests to the 80186.As shipped from the factory, jumpers are installed between

J22-J3 and J22-J4.In this configuration, the (M)USC’s RxREQ drives the 80186 DREQ0 and

(M)USC TxREQ drives the 80186 DREQ1. To reverse this assignment, jumper J22-J1 to J22-J3

andJ22-J2 to J22-J4. To disconnect the (M)USC from one or both of the 80186’s DMA channels,

remove one or both jumpers (put them in a safe place in the event they need to be reinstalled).

ISCC’s Slave Mode Map

(PBA)+128,

130....(PBA)+190

DMA Controller

Registers

(PBA)+192,

194....(PBA)+222

ISCC Serial Channel B

Registers 0-15

(PBA)+224,

226....(PBA)+254

ISCC Serial Channel A

Register 0-15

Advertising
This manual is related to the following products: