Zilog Z80230 - Manual (Page 222)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
215
SRAM Interface
Table has timing parameters for 256 kb SRAM for this design.
256 kb SRAM Key Timing Parameters (Values May Vary Depending On Mfg.)
SRAM Read Cycle
An SRAM read cycle shares the same considerations as an EPROM interface.
Like EPROM, SRAMs’ “access time” applies /G to data valid, and “/E active to data valid” is
shorter than “access time.” This design allows the use of a 150 ns access time SRAM by adding
one wait state (using the on-chip wait state generator of the Z180). The circuit is common to the
EPROM memory read cycle.
/OE to Data Valid 75 75 100
Note: ‘Access Time’ applies /E to data valid. ‘/OE active to data valid’ is shorter than ‘address access time’.
Hence, the interface logic for the EPROM is: Realize a 170 ns or faster EPROM access time by adding one
wait state (using the on-chip wait state generator of the Z180). A 200 ns requirement uses two wait states for
memory access.
Access Time
85 ns
100 ns 150 ns
Parameter Min Min Min
Read Cycle
/E to Data Valid
85 100 150
/G to Data Valid 45 40 60
Write Cycle
Write Cycle Time
85 100 150
Addr Valid to End of Write 75 80 100
Chip Select to End of Write 75 80 100
Data Select to End of Write 40 40 60
Write Pulse Width 60 60 90
Addr Setup Time 0 0 0
Parameter
Access Time
170 ns 200 ns 250 ns
Max Max Max