Zilog Z80230 User Manual

Page 276

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SCC/ESCC

User Manual

UM010903-0515

Application Notes

269

pin is driven from the same signal as CTS. To be compatible with this feature, connect J15-J4 to

pins 4 and 9 of the selected connector among J5-J10.
On the Mac SE, Mac II, and later models, a multiplexing scheme is provided on SCC channel A’s

RTxC pin to drive from either the same signal as DCD, or from an on-board 3.672 MHz clock.

Channel B always had the 3.672 MHz clock. The former capability can be provided by connecting

J15-J6 to pins 6 and 8 of the selected connector among J5-J10. The latter capability can be only

approximated using the 80186 clock with different baud rate divisors, or by using another oscilla-

tor. The board includes an unpopulated 4-pin oscillator socket that can be useful in this regard.

Jumper Summary

Table includes only those connector blocks intended to be populated by 2-pin option jumpers. J1-

J15 and J26 are actual connectors meant for use with cables, jumper wires, or wire wrapped 

connectors.

Two-Pin Option Jumpers

Jumpers

Installed

Open

J9-J7 thru -9

7 to 8: 80186 SYSCLK is IUSC RxC

7 to 9: 80186 SYSCLK is IUSC TxC

8: Something else on RxC, or N/C

9: Something else on TxC, or N/C

J10-J7 thru -9

7 to 8: 80186 SYSCLK is MUSC (USC A) RxC

7 to 9: 80186 SYSCLK is MUSC (USC A) TxC

8: Something else on RxC, or N/C

9: Something else on TxC, or N/C

J12-J7 thru -9

7 to 8: 80186 SYSCLK is USC B RxC

7 to 9: 80186 SYSCLK is USC B TxC

8: Something else on RxC, or N/C

9: Something else on TxC, or N/C

J16-J1 thru -3

1 to 2: J3, J4 TxD driven when RTS

2 to 3: J3, J4 TxD driven full-time

Must install one or the other

J17-J1 thru -2

J17-J3 thru -6

Unbalanced DCD- on J3 or J4

3 to 5 and 4 to 6: CTS+ on J4-J2

3 to 4 and 5 to 6: CTS- on J3 or J4

Differential DCD+,. DCD- on J3

Differential CTS+,. CTS- on J3

J18-J1 thru -3

1 to 2: 2764, 27128, 27256 EPROMs

2 to 3: 27512 EPROMs

Must install one or the other

J19-J1 thru -6

1 to 2 and 4 to 5: 128K x 8 SRAMs

2 to 3 and 5 to 6: 32K x 8 SRAMs

Must install one or the other

J20-J1 thru -3

1 to 2: U2 contains 80C30 or 80230

2 to 3: U2 contains 85C30 or 85230

Must install one or the other

J21-J1 thru -6

1 to 2 and 4 to 5: U2 contains 80C30 or 80230

2 to 3 and 5 to 6: U2 contains 85C30 or 85230

Must install one or the other

J22-J1 thru -4

1 to 2: MUSC (USC A) RxREQ on DMA 0

1 to 3: MUSC (USC A) RxREQ on DMA 1

2 to 4: MUSC (USC A) TxREQ on DMA 0

3 to 4: MUSC (USC A) TxREQ on DMA 1

1: MUSC (USC A) Rx no DMA

4: MUSC (USC A) Tx no DMA

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