Zilog Z80230 - Manual (Page 138)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
131
The secondary station can place its own message on the loop only at specific times. The controller
signals that secondary stations may transmit messages by sending a special character, called an
EOP (End of Poll), around the loop. The EOP character is the bit pattern 11111110.
When a secondary station has a message to transmit and recognizes an EOP on the line, it changes
the last binary 1 of the EOP to a 0 before transmission. This has the effect of turning the EOP into
a flag pattern. The secondary station now places its message on the loop and terminates its mes-
sage with an EOP. Any secondary stations further down the loop with messages to transmit can
append their messages to the message of the first secondary station by the same process.
All secondary stations without messages to send merely echo the incoming messages and are pro-
hibited from placing messages on the loop, except upon recognizing an EOP.
SDLC Loop mode is quite similar to normal SDLC mode except that two additional control bits
are used. Writing a 1 to the Loop Mode bit in WR10 configures the SCC for Loop mode. Writing a
1 to the Go Active on Poll bit in the same register normally causes the SCC to change the next
EOP into a flag and then begin transmitting on loop. However, when the SCC first goes on loop it
uses the first EOP as a signal to insert the one-bit delay, and doesn’t begin transmitting until it
receives the second EOP. There are also two additional status bits in RR10, the On-Loop bit and
the Loop-Sending bit.
There are also restrictions as to when and how a secondary station physically becomes part of the
loop.
A secondary station that has just powered up must monitor the loop, without the one-bit-time
delay, until it recognizes an EOP. When an EOP is recognized the one-bit-time delay is switched
on. This does not disturb the loop because the line is marking idle between the time that the con-
troller sends the EOP and the time that it receives the EOP back. The secondary station that has
gone on-loop cannot place a message on the loop until the next time that an EOP is issued by the
controller. A secondary station goes off loop in a similar manner. When given a command to go
off-loop, the secondary station waits until the next EOP to remove the one-bit-time delay.
To operate the SCC in SDLC Loop mode, the SCC must first be programmed just as if normal
SDLC were to be used. Loop mode is then selected by writing the appropriate control word in
WR10.
The SCC is now waiting for the EOP so that it can go on loop. While waiting for the EOP, the SCC
ties TxD to RxD with only the internal gate delays in the signal path. When the first EOP is recog-
nized by the SCC, the Break/Abort/EOP bit is set in RR0, generating an External/Status interrupt
(if so enabled). At the same time, the On-Loop bit in RR10 is set to indicate that the SCC is indeed
on-loop, and a one-bit time delay is inserted in the TxD to the RxD path.
The SCC is now on-loop but cannot transmit a message until a flag and the next EOP are received.
The requirement that a flag be received ensures that the SCC cannot erroneously send messages
until the controller ends the current polling sequence and starts another one.
If the CPU in the secondary station with the SCC needs to transmit a message, the Go-Active-On-
Poll bit in WR10 is set. If this bit is set when the EOP is detected, the SCC changes the EOP to a
flag and starts sending another flag. The EOP is reported in the Break/Abort/EOP bit in RR0 and