Zilog Z80230 - Manual (Page 142)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
135
processor may either write the first character to the transmit buffer and wait for a transmit buffer
empty condition, or wait for the Break/Abort and Hunt bits to be set in RR10 and the Loop Send-
ing bit to be set in RR10 before writing the first data to the transmitter. The Go-Active-On-Poll bit
should be set to 0 after the transition of the frame has begun. To go off of the loop, the processor
should set the Go-Active-On-Poll bit in WR10 to 0 and then wait for the Loop Sending bit in
RR10 to be set to 0. At this point, the Loop Mode bit (D1) in WR10 is set to 0 to request an orderly
exit from the loop. The SCC exits SDLC Loop mode when seven consecutive 1s have been
received; at the same time the Break/Abort and Hunt bits in RR0 are set to 1, and the On Loop bit
in RR10 is set to 0.