Zilog Z80230 - Manual (Page 146)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
139
The following sections describe WR registers in detail:
Write Register 0 (Command Register)
WR0 is the command register and the CRC reset code register. WR0 takes on slightly different
forms depending upon whether the SCC is in the Z85X30 or the Z80X30. Figure on page 140 dis-
plays the bit configuration for the Z85X30 and includes register select bits in addition to command
and reset codes.
Figure on page 141 displays the bit configuration for the Z80X30 and includes (in Channel B
only) the address decoding select described later.
The following bit description for WR0 is identical for both versions except where specified:
Bits D7 and D6: CRC Reset Codes 1 And 0.
Null Command (00).
This command has no effect on the SCC and is used when a write to WR0 is
necessary for some reason other than a CRC Reset command.
Reset Receive CRC Checker Command (01).
This command is used to initialize the receive
CRC circuitry. It is necessary in synchronous modes (except SDLC) if the Enter Hunt Mode com-
mand in Write Register 3 is not issued between received messages. Any action that disables the
receiver initializes the CRC circuitry. Resetting the Receive CRC Checker command is accom-
plished automatically in SDLC mode.
Reset Transmit CRC Generator Command (10).
This command initializes the CRC generator.
It is usually issued in the initialization routine and after the CRC has been transmitted. A Channel
Reset does not initialize the generator and this command is not issued until after the transmitter
has been enabled in the initialization routine.
On the ESCC and 85C30, this command is not needed if Auto EOM Reset mode is enabled (WR7'
D1=1).
Reset Transmit Underrun/EOM Latch Command (11).
This command controls the transmis-
sion of CRC at the end of transmission (EOM). If this latch has been reset, and a transmit underrun
occurs, the SCC automatically appends CRC to the message. In SDLC mode with Abort on