Zilog Z80230 - Manual (Page 110)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
103
ing the transmission of the CRC, the 16-bit transmission is completed, but the remaining bits will
come from the Sync registers rather than the remainder of the CRC.
There are two modem control signals associated with the transmitter provided by the SCC: /RTS
and /CTS.
The /RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5.
The /CTS pin is ordinarily a simple input to the CTS bit in RR0. However, if Auto Enables mode
is selected, this pin becomes an enable for the transmitter. That is, if Auto Enables is on and the /
CTS pin is High, the transmitter is disabled. While the /CTS pin is Low, the transmitter is enabled.
The initialization sequence for the transmitter in character oriented mode is listed in Table .
At this point, the other registers should be initialized as necessary. When all of this is completed,
the transmitter is enabled by setting bit 3 of WR5 to one. Now that the transmitter is enabled, the
CRC generator is initialized by issuing the Reset Tx CRC Generator command in WR0, bits 6-7.
Byte-Oriented Synchronous Receive
The receiver in the SCC searches for character synchronization only while it is in Hunt mode. In
this mode the receiver is idle except that it is searching the incoming data stream for a sync charac-
ter match.
In Hunt mode, the receiver shifts for each bit into the Receive Shift register. The contents of the
Receive Shift register are compared with the sync character (stored in another register), repeating
the process until a match occurs. When a match occurs, the receiver begins transferring bytes to
the Receive FIFO.
The receiver is in Hunt mode when it is first enabled, and it may be placed in Hunt mode by the
processor issuing the Enter Hunt Mode command in WR3. This bit (D4) is a command, so writing
a 0 to it has no effect. The hunt status of the receiver is reported by the Sync/Hunt bit in RR0.
Sync/Hunt is one of the possible sources of external/status interrupts, with both transitions causing
an interrupt. This is true even if the Sync/Hunt bit is set as a result of the processor issuing the
Enter Hunt Mode command.
Transmitter Initialization in Character Oriented Mode
Reg Bit No Description
WR4 0,1 selects parity (not typically used in sync
modes)
WR5 1 RTS
2 selects CRC generator
5,6 selects number of bits per character
WR10 7 CRC preset value