Zilog Z80230 - Manual (Page 256)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
249
First, this program (Table on page 244) initializes the SCC by Async, X1 mode, 8-bit 1 stop, Non-
parity. Tx and Rx clock from BRG, and BRG set to PCLK/4 Self Loopback. Then, it initializes 4
KB of memory with a repeating pattern beginning with 00h and increases by one to
FFh
(uses this
as Tx buffer area). Also, it begins another 4 KB of memory as a Rx buffer with all zeros. After
starting, DMA initialization follows.
DMAC0:

For Rx data transfer I/O to Mem, Source address- fixed, Destination address-increasing. Edge
sense mode Interrupt on end of transfer.
DMAC1:

For Tx data transfer Mem to I/O, Source address-increasing, Destination address - fixed. Edge
sense mode Interrupt on end of transfer.
Now, start sending with DMA.
On completion of the transfer, the Z180 DMAC1 generates an interrupt. Then, wait for the inter-
rupt from DMAC0 which shows an end of receive. Now, compare received data with sent data. If
the transfer was successful (source data matched with destination),
00h
is left in the accumulator.
If not successful,
0FFh
is left in the accumulator.
This program example specifies a way to initialize the SCC and the Z180 DMA.
Summary
This Application Note describes only one example of implementation, but gives you an idea of
how to design the system using the Z180 and SCC. For further design assistance, a completed
board together with the Debug/Monitor program and the listed sample program are available. For
more information, contact your local Zilog sales office.