Zilog Z80230 - Manual (Page 156)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
149
Bit 5: Auto Enable
This bit programs the function for both the /DCD and /CTS pins. /CTS becomes the transmitter
enable and /DCD becomes the receiver enable when this bit is set to 1. However, the Receiver
Enable and Transmit Enable bits must be set before the /DCD and /CTS pins can be used in this
manner. When the Auto Enable bit is set to 0, the /DCD and /CTS pins are inputs to the corre-
sponding status bits in Read Register 0. The state of /DCD is ignored in the Local Loopback mode.
The state of /CTS is ignored in both Auto Echo and Local Loopback modes.
Bit 4: Enter Hunt Mode
This command forces the comparison of sync characters or flags to assembled receive characters
for the purpose of synchronization. After reset, the SCC automatically enters the Hunt mode
(except asynchronous). Whenever a flag or sync character is matched, the Sync/Hunt bit in Read
Register 0 is reset and, if External/Status Interrupt Enable is set, an interrupt sequence is initiated.
The SCC automatically enters the Hunt mode when an abort condition is received or when the
receiver is enabled.
Bit 3: Receiver CRC Enable
This bit is used to initiate CRC calculation at the beginning of the last byte transferred from the
Receiver Shift register to the Receive FIFO. This operation occurs independently of the number of
bytes in the Receive FIFO. When a particular byte is to be excluded from the CRC calculation, this
bit should be reset before the next byte is transferred to the Receive FIFO. If this feature is used,
care must be taken to ensure that eight bits per character is selected in the receiver because of an
inherent delay from the Receive Shift register to the CRC checker. This bit is internally set to 1 in
SDLC mode and the SCC calculates the CRC on all bits except zeros inserted between the opening
and closing flags. This bit is ignored in asynchronous modes.
Bit 2: Address Search Mode (SDLC)
Setting this bit in SDLC mode causes messages with addresses not matching the address pro-
grammed in WR6 to be rejected. No receiver interrupts occur in this mode unless there is an
address match. The address that the SCC attempts to match is unique (1 in 256) or multiple (16 in
256), depending on the state of Sync Character Load Inhibit bit. Address FFH is always recog-
nized as a global address. The Address Search mode bit is ignored in all modes except SDLC.
Bit 1: SYNC Character Load Inhibit
If this bit is set to 1 in any mode except SDLC, the SCC compares the byte in WR6 with the byte
about to be stored in the FIFO, and it inhibits this load if the bytes are equal. (Caution: this also
occurs in the asynchronous mode if the received character matches the contents of WR6.) The
SCC does not calculate the CRC on bytes stripped from the data stream in this manner. If the 6-bit
sync option is selected while in Monosync mode, the comparison is still across eight bits, so WR6
is programmed for proper operation.
If the 6-bit sync option is selected with this bit set to 1, all sync characters except the one immedi-
ately preceding the data are stripped from the message. If the 6-bit sync option is selected while in
the Bisync mode, this bit is ignored.