Zilog Z80230 - Manual (Page 52)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
45
cuted internally. Like a hardware INTACK cycle, a software acknowledge causes the /INT pin to
return High, the IEO pin to go Low and the IUS latch to be set for the highest priority interrupt
pending.
As when the hardware /INTACK signal is used, a software acknowledge cycle requires that a
Reset Highest IUS command be issued in the interrupt service routine. If RR2 is read from Chan-
nel A, the unmodified vector is returned. If RR2 is read from Channel B, then the vector is modi-
fied to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector (NV)
bits in WR9 are ignored when bit D5 is set to 1.
The Receiver Interrupt
The sources of receive interrupts consist of Receive Character Available and Special Receive Con-
dition. The Special Receive Condition can be subdivided into Receive Overrun, Framing Error
(Asynchronous) or End of Frame (SDLC). In addition, a parity error can be a special receive con-
dition by programming.
As displayed in Figure on page 45, Receive Interrupt mode is controlled by three bits in WR1.
Two of these bits, D4 and D3, select the interrupt mode; the third bit, D2, is a modifier for the var-
ious modes. On the ESCC, WR7' bit D2 affects the receiver interrupt operation mode as well. If
the interrupt capability of the receiver in the SCC is not required, polling may be used. This is
selected by disabling receive interrupts and polling the Receiver Character Available bit in RR0.
When this bit indicates that a received character has reached the exit location (CPU side) of the
FIFO, the status in RR1 should be checked and then the data should be read. If status is checked, it
must be done before the data is read, because the act of reading the data pops both the data and
error FIFOs. Another way of polling SCC is to enable one of the interrupt modes and then reset the
MIE bit in WR9. The processor may then poll the IP bits in RR3A to determine when receive
characters are available.
Write Register 1 Receive Interrupt Mode Control
Receive Interrupt on the ESCC
On the ESCC, one other bit, WR7' bit D2, also affects the interrupt operation.
WR7' D3=0, a receive interrupt is generated when one byte is available in the FIFO. This mode is
selected after reset and maintains compatibility with the SCC. Systems with a long interrupt
D4 D3
WR1
00 Receive Interrupt Disabled
01 Rx INT On First Character or Special Condition
10 Rx INT On All Receive Characters or Special Condition
11 Rx INT On Special Condition Only
D2
Parity is special condition