Zilog Z80230 - Manual (Page 258)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
251
Table lists the conventional descriptions for the power connections.
Processor
The 80186 CPU can operate at speeds up to 
16 MHz. To use the CPU clock for accurate serial bit clocking, a 9.8304 MHz CPU clock can be
used. The crystal connected to the processor is 2X the operating frequency.
The processor’s 1 MB address space is well-filled, if the maximum RAM complement is
installed. Of the integrated Chip Select outputs provided by the 80186, the UCS is used for the
EPROMs and the PCS6-PCS0 outputs are used for the datacom 
controllers. A hardware address decoder is used for the SRAMs instead of the 80186’s LCS and
MCS3-MCS0 outputs because the RAMs must be accessible to the on-chip DMA function of the
ISCC and IUSC as well as the 80186 CPU.
The 80186 CPU does not decodes addresses from external bus masters. Both 8-bit and 16-bit
accesses are provided for RAM. The EPROMs are only accessible to the 80186 CPU.
The 80186’s mid-range memory chip select feature (specifically, the MCS2 output) provides soft-
ware a way to hardware Reset the ISCC, IUSC, and (M)USC. This allows your program to operate
as if it were in a target system starting from Reset, including the initial write to the Bus Configura-
tion Register (BCR).
The 80186’s two integrated DMA channels can be used for any of the four or six serial data
streams in the B side of the (E)SCC and the (M)USC.
The
DMA EPLD
derives requests for the 80186’s two DMA channels from six inputs, two each for
(E)SCC channel B and the one or two channels in the (M)USC.
It asserts DREQ0 and DREQ1 (High) if any of the inputs for that channel is Low, and the 80186 is
not performing an Interrupt Acknowledge cycle.
Jumper blocks J22, J23, J24, and J29 control the assignment of the 80186’s internal DMA control-
lers, including provision for a clipped Tx request which is needed if a standard SCC is installed in
place of the ESCC. Table lists the 80186 DMA Jumper Connections and various possibilities.
If more than one channel among the ESCC B and (M)USC are enabled for one of the 80186’s
internal DMA channels, software must ensure that only one of the enabled devices makes requests
during a given block transfer. This can be done by leaving an entire Receiver or Transmitter idle or
disabled, or by programming the device so that the DMA request is not output on the pin.
Power Connections
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS