Zilog Z80230 - Manual (Page 148)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
141
Write Register 0 in the Z80X30
At the start of the CRC transmission, the Tx Under-run/EOM latch is set. The Reset command can
be issued at any time during a message. If the transmitter is disabled, this command does not reset
the latch. However, if no External Status interrupt is pending, or if a Reset External Status inter-
rupt command accompanies this command while the transmitter is disabled, an External/Status
interrupt is generated with the Tx Underrun/EOM bit reset in RR0.
Bits D5-D3: Command Codes for the SCC.
Null Command (000).
The Null command has no effect on the SCC.
Point High Command (001).
This command effectively adds eight to the Register Pointer (D2-
D0) by allowing WR8 through WR15 to be accessed. The Point High command and the Register
Pointer bits are written simultaneously. This command is used in the Z85X30 version of the SCC.
Note that WR0 changes form depending upon the SCC version. Register access for the Z80X30
version of the SCC is accomplished through direct addressing.
Reset External/Status Interrupts Command (010).
After an External/Status interrupt (a change
on a modem line or a break condition, for example), the status bits in RR0 are latched. This com-
mand re-enables the bits and allows interrupts to occur again as a result of a status change. Latch-
ing the status bits captures short pulses until the CPU has time to read the change.
The SCC contains simple queueing logic associated with most of the external status bits in RR0. If
another External/Status condition changes while a previous condition is still pending (Reset Exter-
D7 D6 D5 D4 D3 D2 D1 D0
Null Code
Null Code
Select Shift Left Mode
Select Shift Right Mode
Write Register 0 (multiplexed bus mode)
Null Code
Null Code
Reset Ext/Status Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
*
0
0
0
0
1
1
1
1
* B Channel Only