Zilog Z80230 User Manual
Page 134
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SCC/ESCC
User Manual
UM010903-0515
Data Communication Modes
127
the status FIFO for verification by the CPU. The CRC checker is automatically reset in prepara-
tion for the next frame which can begin immediately. Since the byte count and status are saved for
each frame, the message integrity can be verified at a later time. Status information for up to 10
frames can be stored before a status FIFO overrun occurs.
If a frame is terminated with an ABORT, the byte count will be loaded to the status FIFO and the
counter reset for the next frame.
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