Zilog Z80230 - Manual (Page 145)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
138
Among these registers, WR9 (Master Interrupt Control and Reset register) can be accessed
through either channel. The RR2 (Interrupt Vector register) returns the interrupt vector modified
by status, if read from Channel B, and written value (without modification), if read from Channel
A.
Channel A has an additional read register which contains all the Interrupt Pending bits (RR3A).
Write Registers.
Eleven write registers are used for control (includes transmit buffer/FIFO); two
for sync character generation/detection; two for baud rate generation. In addition, there are two
write registers which are shared by both channels; one is the interrupt vector register (WR2); the
other is the Master Interrupt and Reset register (WR9).
On the ESCC and 85C30, there is one additional register (WR7') to control enhanced features.
See
Table on page 136 for a summary of Write registers.
Read Registers.
Four read registers indicate status information; two are for baud rate generation;
one for the receive buffer. In addition, there are two read registers which are shared by both chan-
nels; one for the interrupt pending bits; another for the interrupt vector. On the CMOS/ESCC,
there are two additional registers, RR6 and RR7. They are available if the Frame Status FIFO fea-
ture was enabled in the SDLC mode of operation. On the ESCC, there is an “extended read”
option and if its enabled, certain write registers can be read back.
See Table on page 137 for a summary of Read registers.
Write Registers
The SCC write register set in each channel has 11 control registers (includes transmit buffer/
FIFO), two sync character registers, and two baud rate time constant registers. The interrupt con-
trol register and the master interrupt control and reset register are shared by both channels. In addi-
tion to these, the ESCC and 85C30 has a register (WR7'; prime 7) to control the enhancements.
Between 80X30 and 85X30, the variation in register definition is a command decode structure;
Write Register 0 (WR0). The following sections describe in detail each write register and the asso-
ciated bit configuration for each.
RR15 External Status interrupt information
Notes
1. ESCC and 85C30 only.
2. On the ESCC and 85C30, these registers are readable as RR9, RR4, RR5, and
RR11, respectively, when WR7' D6=1. Refer to the description of WR7 Prime for
enabling the extended read capability.
3. This feature is not available on NMOS.
SCC Read Registers (Continued)
Reg Description