Zilog Z80230 - Manual (Page 127)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
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port; the CPU needs time to determine whether or not the last bit of the closing flag has left the
TxD pin. The ESCC has a new feature to deactivate the /RTS signal when the last bit of the closing
flag clears the TxD pin.
If this feature is enabled by setting bit D2 of WR7', and when WR5 bit D1 is reset during the trans-
mission of a SDLC frame, the deassertion of the /RTS pin is delayed until the last bit of the closing
flag clears the TxD pin. The /RTS pin is deasserted after the rising edge of the transmit clock cycle
on which the last bit of the closing flag is transmitted. This implies that the ESCC is programmed
for Flag on Underrun (WR10 bit D2=1) for the /RTS pin to deassert at the end of the frame. (Oth-
erwise, the deassertion occurs when the next flag is transmitted). This feature works independently
of the programmed transmitter idle state. In Synchronous modes other than SDLC, the /RTS pin
immediately follows the state programmed into WR5 D1. Note that if the /RTS pin is connected to
one of the general purpose inputs (/CTS or /DCD), it can be used to generate an external status
interrupt when a frame is completely transmitted.
NRZI forced High after closing flag:
On the CMOS/NMOS version of the SCC in the SDLC
mode of operation with NRZI mode of encoding and mark idle (WR10 bit D6=0, D5=1, D3=1),
the state of the TxD pin after transmission of the closing flag is undetermined, depending on the
last data sent. With the ESCC in the same operation mode (SDLC, NRZI, with mark idle), the TxD
pin is automatically forced High on the falling edge of the TxC of the last bit of the closing flag,
and then the transmitter goes to the mark idle state.
There are several different ways for a transmitter to go into the idle state. In each of the following
cases, the TxD pin is forced High when the mark idle condition is reached; data, CRC (2 bytes),
flag and idle; data, flag and idle; data, abort (on underrun) and idle; data, abort (by command) and
idle; idle, flag and command to idle mark. The force High feature is disabled when the mark idle
bit is reset (programmed as mark idle). This feature is used in combination with the automatic
SDLC opening flag transmission feature, WR7' bit D0=1, to assure that data packets are properly
formatted. When these features are used together, it is not necessary for the CPU to issue any com-
mands after sending a closing flag in combination with NRZI data encoding. (On the NMOS/
CMOS version, this is accomplished by channel reset, followed by re-initializing the channel). If
WR7' bit D0 is reset, like in the NMOS/CMOS version, it is necessary to reset the mark idle bit
(WR10, bit D3) to enable flag transmission before a SDLC packet is transmitted.
SDLC Receive
The receiver in the SCC always searches the receive data stream for flag characters in SDLC
mode. Ordinarily, the receiver transfers all received data between flags to the receive data FIFO.
However, if the receiver is not in Hunt mode no data is received. The receiver is in Hunt mode
when first enabled, or the receiver is placed in Hunt mode by the processor issuing the Enter Hunt
mode command in WR3. This bit (D4) is a command, and writing a 0 to it has no effect. The Hunt
status of the receiver is reported by the Sync/Hunt bit in RR0.
Sync/Hunt is one of the possible sources of external/status interrupts, with both transitions causing
an interrupt. This is true even if the Sync/Hunt bit is set as a result of the processor issuing the
Enter Hunt mode command.