Zilog Z80230 - Manual (Page 101)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
94
An additional bit, carrying parity information, may be automatically appended to every transmit-
ted character by setting bit D0 of WR4 to 1. This bit is sent in addition to the number of bits spec-
ified in WR4 or by bit D1 of WR4. If this bit is set to 1, the transmitter sends even parity and, if set
to 0, the parity is odd.
The transmitter may be programmed to send a Break by setting bit D4 of WR5 to 1. The transmit-
ter will send contiguous 0s from the first transmit clock edge after this command is issued, until
the first transmit clock edge after this bit is reset. The transmit clock edges referred to here are
those that defined transmitted bit cell boundaries. Care must be taken when Break is sent. As men-
tioned above, the SCC initiates the Break sequence regardless of the character boundaries. Typi-
cally, the break sequence is defined as “null character (all 0 data) with framing error”. The other
party may not be able to recognize it as a break sequence if the Send Break bit has been set in the
middle of sending a non-zero character.
An additional status bit for use in Asynchronous mode is available in bit D0 of RR1. This bit,
called All Sent, is set when the transmitter is completely empty and any previous data or stop bits
have reached the TxD pin. The All Sent bit can be used by the processor as an indication that the
transmitter may be safely disabled, or indication to change the modem status signal.
Transmit Bits per Character
Bit 7 Bit 6
0 0 5 or less bits/
character
0 1 7 bits/character
1 0 6 bits/character
1 1 8 bits/character
Note: For five or less bits per character selection in WR5,
the following encoding is used in the data sent to the trans-
mitter. D is the data bit(s) to be sent.
D7 D6 D5 D4 D3 D2 D1 D0
1
1 1 1 0 0 0 D Sends one data bit
1 1 1 0 0 0 D D Sends two data bits
1 1 0 0 0 D D D Sends three data bits
1 0 0 0 D D D D Sends four data bits0
0 0 0 D D D D D Sends five data bits