Zilog Z80230 - Manual (Page 237)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
230
This circuit depicts logic for the I/O interface and the Interrupt Acknowledge Interface for 10
MHz clock of operation. Figure on page 230 is the I/O read/write timing chart (discussions of
timing considerations on the Interrupt Acknowledge cycle and the circuit using EPLD occur later).
SCC I/O Read/Write Cycle Timing
This circuit works when [(Lower HCT164’s CLK. to Z180 /WAIT.) + tws <tCHW]. If you are run-
ning your system slower than 8 MHz, remove the HCT74, D-Flip/Flop in front of HCT164. Con-
nect the inverted CSSCC to the HCT164 B input. This is a required Flip/Flop because the Z180
timing specification on tIOD1 (Clock High to /IORQ Low, IOC=0) is maximum at 55 ns This is
longer than half the PHI clock cycle. Sample it using the rising edge of clock, otherwise, HCT164
does not generate the same signals.
The RESET signal feeds the SCC /RD and /WR through HCT27 and HCT02 to supply the hard-
ware reset signal. To reduce the gate count, drop these gates and make the SCC reset by its soft-
ware command. The SCC software reset–0C0h to Write Register 9, “Hardware Reset command”
has the same effect as hardware reset by “Hardware.”