Zilog Z80230 - Manual (Page 248)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
241
There is one good test to ensure proper function. Generate a data transfer between the Z180/SCC
using the Z180 onchip DMA. The SCC self loop-back test transfers data using the Z180 DMA at
the highest transmission rate.
Program Example – Z180 CPU Macro Instructions
;* File name - 180macro.lib
;* Macro library for Z180 new instructions for asm800
;*
;
;Z180 System Control Registers
;ASCI Registers
cntla0: equ 00h ; ASCI Cont Reg A Ch0
cntla1: equ 01h ; ASCI Cont Reg A Ch1
cntlb0: equ 02h ; ASCI Cont Reg B Ch0
cntlb1: equ 03h ; ASCI Cont Reg B Ch1
stat0: equ 04h ; ASCI Stat Reg Ch0
stat1: equ 05h ; ASCI Stat Reg Ch1
tdr0: equ 06h ; ASCI Tx Data Reg Ch0
tdr1: equ 07h ; ASCI Tx Data Reg Ch1
rdr0: equ 08h ; ASCI Rx Data Reg Ch0
rdr1: equ 09h ; ASCI Rx Data Reg Ch1
;CSI/O Registers
cntr: equ 0ah ; CSI/O Cont Reg
trdr: equ 0bh ; CSI/O Tx/Rx Data Reg
;Timer Registers
tmdr0l: equ 0ch ; Timer Data Reg Ch0-low
tmdr0h: equ 0dh ; Timer Data Reg Ch0-high
rldr0l: equ 0eh ; Timer Reload Reg Ch0-low
rldr0h: equ 0fh ; Timer Reload Reg Ch0-high
tcr: equ 10h ; Timer Cont Reg
tmdr1l: equ 14h ; Timer Data reg Ch1-low
tmdr1h: equ 15h ; Timer Data Reg Ch1-high
rldr1l: equ 16h ; Timer Reload Reg Ch1-low
rldr1h: equ 17h ; Timer Reload Reg Ch1-high
frc: equ 18h ; Free Running Counter
;DMA Registers
sar0l: equ 20h ; DMA Source Addr Reg Ch0-low
sar0h: equ 21h ; DMA Source Addr Reg Ch0-high
sar0b: equ 22h ; DMA Source Addr Reg Ch0-b
dar0l: equ 23h ; DMA Dist Addr Reg Ch0-low
dar0h: equ 24h ; DMA Dist Addr Reg Ch0-high
dar0b: equ 25h ; DMA Dist Addr Reg Ch0-B
bcr0l: equ 26h ; DMA Byte Count Reg Ch0-low
bcr0h: equ 27h ; DMA Byte Count Reg Ch0-high
mar1l: equ 28h ; DMA Memory Addr Reg Ch1-low
mar1h: equ 29h ; DMA Memory Addr Reg Ch1-high
mar1b: equ 2ah ; DMA Memory Addr Reg Ch1-b
iar1l: equ 2bh ; DMA I/O Addr Reg Ch1-low
iar1h: equ 2ch ; DMA I/O Addr Reg Ch1-high